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Freescale Semiconductor Technical Data
MC144110/D Rev. 2, 1/2005
MC144110
MC144110 and MC144111
Digital-to-Analog Converters with Serial Interface
CMOS LSI
Package Information P Suffix Plastic DIP Case 707
Package Information DW Suffix SOG Package Case 751D
MC144111
1
Introduction
The MC144110 and MC144111 are low-cost 6-bit D/A converters with serial interface ports to provide communication with CMOS microprocessors and microcomputers. The MC144110 contains six static D/A converters; the MC144111 contains four converters. Due to a unique feature of these DACs, the user is permitted easy scaling of the analog outputs of a system. Over a 5 to 15 V supply range, these DACs may be directly interfaced to CMOS MPUs operating at 5 V. * * * * * * * * Direct R-2R Network Outputs Buffered Emitter-Follower Outputs Serial Data Input Digital Data Output Facilitates Cascading Direct Interface to CMOS P Wide Operating Voltage Range: 4.5 to 15 V Wide Operating Temperature Range: 0 to 85C Software Information is Contained in Document M68HC11RM/AD
Package Information P Suffix Plastic DIP Case 646
Package Information DW Suffix SOG Package Case 751G
Ordering Information Device MC144110P MC144110DW MC144111P MC144111DW Package Plastic DIP SOG Plastic DIP SOG
Contents
1 2 3 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Specifications . . . . . . . . . . . . . . . . 4 Switching Characteristics . . . . . . . . . . . . . . . 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2005. All rights reserved.
Introduction
VDD
Q1 OUT
Rn Qn R1 OUT OUT OUT
2R R 2R 2R R 2R R 2R R 2R R 2R
HEX BUFFER (INVERTING)
ENB
C
HEX LATCH
CLK
C
*
C D 6-BIT SHIFT REGISTER Dout
DQ Din
*Transparent Latch Figure 1. Block Diagram
MC144110 Technical Data, Rev. 2 2 Freescale Semiconductor
Introduction
MC144110P
Din Q1 Out R1 Out Q2 Out R2 Out Q3 Out R3 Out ENB VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD Dout R6 Out Q6 Out R5 Out Q5 Out R4 Out Q4 Out CLK Din Q1 Out R1 Out Q2 Out R2 Out Q3 Out R3 Out ENB VSS NC
MC144110DW
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Dout R6 Out Q6 Out R5 Out Q5 Out R4 Out Q4 Out CLK NC
MC144111P
Din Q1 Out R1 Out Q2 Out R2 Out ENB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD Dout R4 Out Q4 Out R3 Out Q3 Out CLK Din Q1 Out R1 Out Q2 Out R2 Out ENB VSS
MC144111DW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Dout R4 Out Q4 Out R3 Out Q3 Out CLK NC
NC = No Connection
Figure 2. Pin Assignments
MC144110 Technical Data, Rev. 2 Freescale Semiconductor 3
Electrical Specifications
2
Electrical Specifications
Table 1. Maximum Ratings (Voltages referenced to VSS)
Ratings Symbol VDD Vin I POH 30 50 10 20 PD 100 150 25 50 Tstg - 65 to + 150 C mW Value - 0.5 to + 18 - 0.5 to VDD + 0.5 10 Unit V V mA mW
DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation (Per Output) TA = 70C MC144110 MC144111 TA = 85C MC144110 MC144111 Power Dissipation (Per Package) TA = 70C MC144110 MC144111 TA = 85C MC144110 MC144111 Storage Temperature Range
This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
Table 2. Electrical Characteristics (Voltages referenced to VSS, TA = 0 to 85C unless otherwise indicated)
Symbol VIH Parameter High-Level Input Voltage (Din, ENB, CLK) Test Conditions VDD 5 10 15 5 10 15 Vout = VDD - 0.5 V Vout = 0.5 V MC144110 MC144111 Iout = 0 A Vin = VDD or 0 V See Figure 3 5 5 15 15 15 5 10 15 Min 3.0 3.5 4 - 200 200 Max 0.8 0.8 0.8 12 8 1 100 200 300 Unit V
VIL
Low-Level Input Voltage (Din, ENB, CLK)
V
IOH IOL IDD Iin Vnonl
High-Level Output Current (Dout) Low-Level Output Current (Dout) Quiescent Supply Current
A A mA A mV
Input Leakage Current (Din, ENB, CLK) Nonlinearity Voltage (Rn Out)
MC144110 Technical Data, Rev. 2 4 Freescale Semiconductor
Switching Characteristics
Table 2. Electrical Characteristics (continued) (Voltages referenced to VSS, TA = 0 to 85C unless otherwise indicated)
Symbol Vstep Step Size (Rn Out) Parameter Test Conditions See Figure 4 VDD 5 10 15 15 Min 19 39 58 40 0.4 Max 137 274 411 1 10 0.7 Unit mV
Voffset IE hFE VBE
Offset Voltage from VSS Emitter Leakage Current DC Current Gain Base-to-Emitter Voltage Drop
Din = $00, See Figure 3 VRn Out = 0 V IE = 0.1 to 10.0 mA TA = 25C IE = 1.0 mA
LSB A V
3
Switching Characteristics
Table 3. Switching Characteristics (Voltages referenced to VSS, TA = 0 to 85C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated)
Symbol twH
Parameter Positive Pulse Width, CLK (Figures 5 and 6)
VDD 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 - 15 5 - 15
Min 2 1.5 1 5 3.5 2 5 3.5 2 1000 750 500 5 3.5 2 5 3.5 2 -
Max 2 7.5
Unit s
twL
Negative Pulse Width, CLK (Figure 5 and 6)
s
tsu
Setup Time, ENB to CLK (Figures 5 and 6)
s
tsu
Setup Time, Din to CLK (Figures 5 and 6)
ns
th
Hold Time, CLK to ENB (Figures 5 and 6)
s
th
Hold Time, CLK to Din (Figures 5 and 6)
s
tr, tf Cin
Input Rise and Fall Times Input Capacitance
s pF
MC144110 Technical Data, Rev. 2 Freescale Semiconductor 5
Switching Characteristics
100 OUTPUT VOLTAGE @ Rn Out, % (VDD - VSS)
75
Vnonl
50
IDEAL ACTUAL
25
Voffset
0 0 $00 15 $0F 31 $1F PROGRAM STEP LINEARITY ERROR (integral linearity). A measure of how straight a device's transfer function is, it indicates the worst-case deviation of linearity of the actual transfer function from the best-fit straight line. It is normally specified in parts of an LSB. 47 $2F 63 $3F
Figure 3. D/A Transfer Function
VRn OUT
STEP SIZE
V DD V DD Step Size = ----------- 0.75 ----------64 64 (For any adjacent pair of digital numbers)
DIGITAL NUMBER
Figure 4. Definition of Step Size
MC144110 Technical Data, Rev. 2 6 Freescale Semiconductor
Switching Characteristics
50% ENB tsu 50% C1 twH twL C2 CN th
CLK
Din tsu
D1 th
D2
DN
Figure 5. Serial Input, Positive Clock
ENB th C1 twL twH C2 CN
tsu CLK
Din
D1 tsu
D2 th
DN
Figure 6. Serial Input, Negative Clock Table 4. Number of Channels vs Clocks Required
Number of Channels Required 1 2 3 4 5 6 Number of Clock Cycles 6 12 18 24 30 36 Q1/R1 Q1/R1, Q2/R2 Q1/R1, Q2/R2, Q3/R3 Q1/R1, Q2/R2, Q3/R3, Q4/R4 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5, Q6/R6 Outputs Used on MC144110 Outputs Used on MC144111 Q1/R1 Q1/R1, Q2/R2 Q1/R1, Q2/R2, Q3/R3 Q1/R1, Q2/R2, Q3/R3, Q4/R4 Not Applicable Not Applicable
MC144110 Technical Data, Rev. 2 Freescale Semiconductor 7
Pin Descriptions
4
4.1
Pin Descriptions
INPUTS
Din Data Input
Six-bit words are entered serially, MSB first, into digital data input, Din. Six words are loaded into the MC144110 during each D/A cycle; four words are loaded into the MC144111. The last 6-bit word shifted in determines the output level of pins Q1 Out and R1 Out. The next-to-last 6-bit word affects pins Q2 Out and R2 Out, etc.
ENB Negative Logic Enable
The ENB pin must be low (active) during the serial load. On the low-to-high transition of ENB, data contained in the shift register is loaded into the latch.
CLK Shift Register Clock
Data is shifted into the register on the high-to-low transition of CLK. CLK is fed into the D-input of a transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high. The number of clock cycles required for the MC144110 is usually 36. The MC144111 usually uses 24 cycles. See Table 4 for additional information.
4.2
OUTPUTS
Dout Data Output
The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage.
R1 Out through Rn Out Resistor Network Outputs
These are the R-2R resistor network outputs. These outputs may be fed to high-impedance input FET op amps to bypass the on-chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 k.
MC144110 Technical Data, Rev. 2 8 Freescale Semiconductor
Pin Descriptions
Q1 Out through Qn Out NPN Transistor Outputs
Buffered DAC outputs utilize an emitter-follower configuration for current-gain, thereby allowing interface to low-impedance circuits.
4.3
SUPPLY PINS
VSS Negative Supply Voltage
This pin is usually ground.
VDD Positive Supply Voltage
The voltage applied to this pin is used to scale the analog output swing from 4.5 to 15 V p-p.
MC144110 Technical Data, Rev. 2 Freescale Semiconductor 9
Packaging
5
Packaging
J
18 1 10
B
9
L
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D). SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH.
A C
M
DIM A B C D F G H J K L M N
N F H G D
K
SEATING PLANE
INCHES MILLIMETERS MIN MAX MIN MAX 0.875 0.915 22.22 23.24 0.240 0.260 6.10 6.60 0.140 0.180 3.56 4.57 0.014 0.022 0.36 0.56 0.050 0.070 1.27 1.78 0.100 BSC 2.54 BSC 0.040 0.060 1.02 1.52 0.008 0.012 0.20 0.30 0.115 0.135 2.92 3.43 0.300 BSC 7.62 BSC 0 15 0 15 0.020 0.040 0.51 1.02
Figure 7. Outline Dimensions for P SUFFIX, PLASTIC DIP (CASE 707-02, Issue C)
10X PIN NUMBER
10.55 10.05 0.25 M B
2.65 2.35 A 0.25 0.10
20X
1
20
0.49 0.35 0.25
6
M
TAB
PIN 1 INDEX
18X
1.27
4 12.95 12.65 A A
10
11
T
20X
SEATING PLANE
7.6 7.4 5
B
0.1 T
0.75 0.25
X45
0.32 0.23
1.0 0.4 SECTION A-A
7 0
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE WIDTH TO EXCEED 0.62mm.
Figure 8. Outline Dimensions for DW SUFFIX, SOG (CASE 751D-06, Issue H)
MC144110 Technical Data, Rev. 2 10 Freescale Semiconductor
Packaging
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 6. 646-06 OBSOLETE, NEW STANDARD 646-07. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.040
A F N -TSEATING PLANE
L C
K H G D 14 PL (0.005)
M
J
M
DIM A B C D F G H J K L M N
Figure 9. Outline Dimensions for P SUFFIX, PLASTIC DIP (CASE 646-07, Issue P)
0.25
PIN'S NUMBER 1 PIN 1 INDEX 8X
M
B A
10.55 10.05
16
2.65 2.35
0.25 0.10
16X
0.49 0.35 0.25
6
M
TAB
14X
A
8 9
10.45 4 10.15 A
1.27
7.6 7.4 5
T B
16X
SEATING PLANE
0.1 T
0.75 0.25
X45
0.32 0.23
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm.
1.0 0.4 SECTION A-A
7 0
Figure 10. Outline Dimensions for DW SUFFIX, SOG (CASE 751G-04, Issue D)
MC144110 Technical Data, Rev. 2 Freescale Semiconductor 11
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MC144110/D Rev. 2 1/2005

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